Memory Statistics Information System (MSIS)

Hardware evaluation platforms for emerging memory technologies, called Memory Statistics Information System (MSIS) are one of the Myoungsoo's ongoing projects. The main purpose behind this prototype project is to measure intrinsic latency variation and better understand emerging non-volatile memory systems in order to build more reasonable and detailed non-volatile simulation models. Even though modern non-volatile memory systems employ quite complex mechanisms, parallel internal components and have many reliability issues, academia still use constant values and latency approximation model for simulation. One of the reason behind that academia simulation models are oblivious of modern non-volatile memory is that non-volatile memory maker hide their internal technologies and behaviors.

MSIS can capture fine-grained latencies (in nanosecond scale), voltages, current, and reliability issues (e.g., I/O disturbance problems, bit errors on physical pages, endurance problem) for following emerging non-volatile memory types: 

 1. Single-Level Cell NAND flash 
 2. Multi-Level Cell NAND flash 
 3. Triple-Level Cell NAND flash
 4. Phase-change RAM (PCRAM - Numonix) 
 5. Magnetic RAM (MRAM - Everspin)

In addition, the MSIS extension hardware prototype employs multiple channels, flash buses and multiple cores. Unlike other hardware platform, this prototype includes a sudden power-off (SPO) recovery test sub-system. This sub-system reveals not only reliability problems affected by physical non-volatile memory characteristics but also memory failure behaviors caused by various system software on SPO situations.

The main hardware features are as follows:

  • Samsung S3C2440 ARM-based processor(s)
  • ATTINY2313 sub-controller (for SPO recovery tests)
  • TSOP-type 48 pin interfaces
  • H57V2562GTR, SK Hynix Synchronous DRAM
    • 268,435,456bit CMOS Synchronous DRAM * 2
    • 4banks of 4,194,304 x 16 I/O
  • S29AL01657TE102 Spansion embedded NOR flash (for flash software such as buffer cache, flash translation layer, and flash interface driver)
  • K9F2G08U08 Samsung NAND flash (for persistent meta data of flash software)



MSIS Hardware Prototypes for NAND Flash



Multi-channel and -core Prototype



Phase-change RAM and Magnetic RAM Hardware Prototypes



Schematics

Main Controller


The above diagram pictorially illustrates external pins configuration of S3C2440. Such pins of the S3C2440 are interfaced for NV memory adopters, and connected to ATTINY2313 to control power of such NV memory devices. Specifically, the S3C2440 pins that assigned to memory adopters are selectively used and activated based on which type of NV memory devices will be used for evaluation.

Sudden Power Off (SPO) Testing Subsystem

The S3C2440 main controller, ATTINY2313 (5V) and NV memory devices (3.3V) are transformed from same voltage source (12V) by 7805 and 78R33 regulator, respectively.

As shown in the above schematic, ATTINY2313 controls power sources of both S3C2440 and NV memory devices. ATTINY2313 is able to perform the sudden power off recovery (SPOR) test for them at the same time, and also it can perform the SPOR for each device in an independent way.