CAMEL designs and validates modular AI datacenter fabrics that connect processors, accelerators, memory, and storage as composable resources. Our work spans silicon-proven low-latency CXL controllers, port-based fabric switches, memory expansion and pooling, GPU memory scaling, and software stacks for real applications. We also study how CXL can work with accelerator-centric links such as UALink and NVLink and with high-bandwidth memory to reduce communication and memory-capacity bottlenecks in large-scale AI and HPC systems.

Modern AI services move large models, embeddings, KV caches, checkpoints, and graph data through memory and storage hierarchies. We build computational memory and storage systems that place data preparation and processing close to the data. Current work includes in-storage RAG acceleration, host-free checkpointing for multimodal LLM training, hardware-driven GNN preprocessing, ML-aware SSD reliability, and CXL-enabled storage disaggregation. Our goal is to reduce data movement while improving end-to-end performance, energy efficiency, and reliability.

We turn emerging-memory concepts into deployable hardware/software systems. Our research prototypes combine computational-memory SoCs, chiplet-based components, FPGA/RTL controllers, near-data processing datapaths, and Linux-compatible software stacks. We validate these systems with LLM, RAG, recommendation, graph, and datacenter workloads so architectural ideas can be measured on real platforms rather than only through simulation.

AI and data-intensive applications increasingly combine CPUs, GPUs, FPGAs, domain-specific accelerators, and disaggregated memory. We co-design hardware and software to minimize data movement, accelerate preprocessing and inference, and coordinate heterogeneous resources through coherent links and memory-centric interfaces. Current projects include GNN acceleration, computational SSDs, GPU memory expansion, and low-power accelerator/memory integration.

We study emerging NVM devices and systems across characterization, controllers, persistence, reliability, and system integration. Our work covers RRAM, phase-change memory, STT-MRAM, NAND flash, and other low-latency or byte-addressable technologies, with an emphasis on prototypes and applications that reveal where each technology provides real system-level value.

Datacenter SSD behavior depends on firmware, controllers, operating-system policies, and workload characteristics. We design hardware/software mechanisms for predictable performance, reliability, endurance, thermal management, I/O scheduling, garbage collection, and in-storage processing. Recent work includes ML-aware reliability hints, next-generation SSD arrays, ZNS all-flash arrays, and containerized computational storage.

Memory capacity, communication, and data movement increasingly limit AI and HPC workloads. We study memory-centric system architectures that combine disaggregated memory, computational storage, checkpointing, and near-data acceleration to improve performance and energy efficiency. Our designs target scientific computing as well as modern LLM, graph, and recommendation workloads.

High-performance storage systems must exploit parallelism across devices, channels, chips, queues, and distributed resources while controlling latency and endurance. We investigate user-space all-flash arrays, ZNS storage, scalable I/O stacks, CXL-connected storage, and controller scheduling techniques that coordinate system-level and device-level parallelism.

Reliable evaluation requires fast, accurate, and reproducible tools that span applications, system software, controllers, and devices. We build open simulation frameworks, FPGA-based emulators, trace collections, and hardware validation platforms for SSDs, NVM, memory systems, and accelerators. These tools support hardware/software co-design and enable researchers to reproduce results across the full system stack.

Modern datacenter SSDs exhibit workload-dependent latency, endurance, thermal, reliability, and interference behavior. We characterize these effects on real devices and use the results to guide operating-system policies, controller design, storage arrays, and ML-aware reliability management. The goal is to replace outdated assumptions with measurements that reflect current flash technologies and deployment environments.